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ds07-16704-1e fujitsu semiconductor data sheet copyright?2007 fujitsu li mited all rights reserved ?check sheet? is seen at the following support page url : http://www.fujitsu.com/global/services/micr oelectronics/product/micom/support/index.html ?check sheet? lists the minimal require ment items to be checked to prev ent problems beforehand in system development. be sure to refer to the ?check sheet? for the latest cautions on development. 32-bit microcontroller cmos fr60 lite mb91345 series mb91f345b/f346b description the mb91345 series is the microcontrollers based on 32- bit high-perform risc-cpu while integrating a variety of i/o resources for embedded control applications whic h require high-performance, high-speed cpu processing. it is suitable for the embedded control in digital home appliances or audio visual equipment, requiring high- performance cpu processing power. this product compactly integrates a variety of peripheral f unctions for single chip and is fr60 applicable to faster- speed application. note : fr, the abbreviation of fujitsu risc co ntroller, is a line of products of fujitsu limited. feature ? fr cpu 32-bit risc, load/store architecture, with a five-stage pipeline maximum operating frequency : 50 mhz [pll used : original oscillation 12.5 mhz] 16-bit fixed length instruction (basic instructions) ; 1 instruction per cycle instruction set optimized for embedded applications : memory-to-memory transfer, bit manipulation, barrel shift instructions instructions adapted for high-level programming language s : function entry/exit instructions, multiple-register load/store instructions register interlock function : facilitating coding in assembles (continued)
mb91345 series 2 on-chip multiplier supported at instruction level signed 32-bit multiplication : 5 cycles signed 16-bit multiplication : 3 cycles interrupt (pc, ps save) : 6 cycles, 16 priority levels harvard architecture allowing program access and data access to be executed simultaneously instruction set compatible with fr family ? external bus interface operating frequency : max 25 mhz 24-bit address full output (16 mbytes area) 8/16-bit data output capable of chip-select signal output for completely independent four areas settable in 64 kbytes minimum support for various memory interfaces : sram and rom/flash basic bus cycle : 2 cycles programmable automatic wait cycle generator capable of inserting wait cycles for each area external wait cycles generated by rdy input unused data/address pins can serve for general-purpose i/o ? internal memory ? dmac (dma controller) 5 channels two transfer factors (internal peripheral / software) addressing mode : 20/24-bit full-address selection (increment/decrement/fixed) transfer modes (burst transfer/step transfer/and block transfer) selectable transfer data sizes : 8, 16, or 32 bits ? bit search module (for realos) search for the position of the bit i/o- changed first in one word from the msb ? reload timer : 3 channels (including 1channel for realos) 16-bit timer the internal clock is optional from 2/8/32 division ? multi function serial interface 11 channels full duplex double buffer 2 channels out of 11 channels with 16-byte fifo capable of selecting communication mode : asynch ronous (start-stop synchronous) communication, clock synchronous communication (max 8.25 mbps) , i 2 c* standard mode (max 100 kbps) , high-speed mode (max 400 kbps) parity on/off selectable baud rate generator per channel abundant error detection functions are pr ovided (parity, frame, and overrun) external clock can be used as transfer clock ch.0, ch.1, ch.2, and ch.10 is tolerant of 5 v (continued) flash d-bus ram f-bus ram mb91f345b 512 kbytes 24 kbytes 8 kbytes mb91f346b 1 mbyte 24 kbytes 8 kbytes
mb91345 series 3 (continued) ? interrupt controller a total of 24 external interrupt lines (external interrupt pins int23 to int0) interrupt from internal peripheral programmable 16 priority levels available for wakeup from stop mode ? a/d converter : 10-bit resolution, 8 channels + 8 channels 2unit successive approximation type : conversion time : min. 1.2 s (at 16 mhz) conversion mode (shingle-shot conver sion mode, scan conversion mode) startup source (software/external trigger) ? ppg timer : up to 16 channels (at 8 bits) 8/16-bit ppg timer : 8 bits 16 channels or 16 bits 8 channels the internal clock is optional from 1/4/16/64 division ? pwc timer : 1 channel 16-bit up counter 1 channel (1 input) ? input capture and output compare : up to 8 channels (ch.0 to ch.3; 16-bit ic u, ocu, ch.4 to ch.7; 32-bit icu, ocu) 16-bit free-run counter 1 channel + 16-bit input capture 4 channels + 16-bit output compare 4 channels 32-bit free-run counter 1 channel + 32-bit input capture 4 channels + 32-bit output compare 4 channels ? min/max/abs min/max/abs is performed and the re sult is accumulated and added. ? other interval timer and counter 8/16-bit up down counter : 8-bit 4 channels or 16-bit 2 channels 16-bit timebase timer/watchdog timer ? i/o port max 71 ports ? other features internal oscillation circuit as a clock source and pll multiplier init is prepared as a reset terminal watchdog timer reset and software reset are also available stop and sleep mode support ed as low-power-consumption modes gear function built-in time base timer memory patch function package : tqfp-100 cmos technology (0.18 m) power supply voltage : 3.3 v 0.3 v (single power supply) * : purchase of fujitsu i 2 c components conveys a license under the philips i 2 c patent rights to use, these components in an i 2 c system provided that th e system conforms to the i 2 c standard specification as defined by philips.
mb91345 series 4 pin assignment note : totx and totx-2 have same func tion. also adtrgx and adtrgx-2 have same function. use either of the tw o depending on the combined resource. vcc p2 3 /a0 3 / s in1 p22/a02/ s ck0 p21/a01/ s ot0 p20/a00/ s in0 p17/d15/adtrg0 p16/d14/ s ck7/adtrg1 p15/d1 3 / s ot7/tot2 p14/d12/ s in7/tin2 p1 3 /d11/ s ck6/tot1 p12/d10/ s ot6/tin1 p11/d09/ s in6/tot0 p10/d0 8 / s ck5/tin0 p07/d07/ s ot5/int15 p06/d06/ s in5/int14 p05/d05/ s ck4/int1 3 p04/d04/ s ot4/int12 p0 3 /d0 3 / s in4/int11 p02/d02/ s ck 3 /int10 p01/d01/ s ot 3 /int9 p00/d00/ s in 3 /int 8 p6 3 / s y s clk/rt 3 p62/rdy/rt2/adtrg1-2 p61/rt1/pwc0/adtrg0-2 vcc 100 99 9 8 97 96 95 94 9 3 92 91 90 8 9 88 8 7 8 6 8 5 8 4 83 8 2 8 1 8 0 79 7 8 77 76 1 75 v ss 2 74 p60/rt0 3 7 3 p57/wr1/rt7 4 72 p56/wr0/rt6 5 71 p55/rd/rt5 6 70 p54/a s /rt4 7 69 p5 3 /c s3 /ppg7 8 6 8 p52/c s 2/ppg5 9 67 p51/c s 1/ppg 3 10 66 p50/c s 0/ppg1 11 65 md2 12 64 md1 1 3 6 3 md0 14 62 init 15 61 tr s t 16 60 ibreak 17 59 ic s 2 1 8 5 8 ic s 1 19 57 ic s 0 20 56 icd 3 21 55 icd2 22 54 icd1 2 3 5 3 icd0 24 52 iclk 25 51 vcc 26 27 2 8 29 3 0 3 1 3 2 33 3 4 3 5 3 6 3 7 38 3 9 40 41 42 4 3 44 45 46 47 4 8 49 50 vcc pd0/an0/ain1 pd1/an1/bin1 pd2/an2/zin1 pd 3 /an 3 /ain 3 pd4/an4/bin 3 pd5/an5/zin 3 /ppg0 pd6/an6/ppg2 pd7/an7/ppg4 avcc avrh avrl av ss pe0/an 8 /int0/ppg6 pe1/an9/int1/ppg 8 pe2/an10/int2/ppga pe 3 /an11/int 3 /ppgc pe4/an12/int4/ppge pe5/an1 3 /int5/ s in 8 pe6/an14/int6/ s ot 8 pe7/an15/int7/ s ck 8 pc0/frck0/ s in9 pc1/ic6/ s ot9 pc2/ic7/ s ck9 v ss v ss c p24/a04/ s ot1 p25/a05/ s ck1 p26/a06/ s in2 p27/a07/ s ot2 p 3 0/a0 8 / s ck2 p 3 1/a09/ain0/tot0-2 p 3 2/a10/bin0/tot1-2 p 33 /a11/zin0/tot2-2 p 3 4/a12/ain2 p 3 5/a1 3 /bin2/ic4 p 3 6/a14/zin2/ic5 p 3 7/a15/frck1 p40/a16/ppg9/int16 p41/a17/ppgb/int17 p42/a1 8 /ppgd/int1 8 p4 3 /a19/ppgf/int19 p44/a20/ic0/int20 p45/a21/ic1/int21/ s in10 p46/a22/ic2/int22/ s ot10 p47/a2 3 /ic 3 /int2 3 / s ck10 v ss x1 x0 (top view) (fpt-100p-m18)
mb91345 series 5 pin description (continued) pin no. pin name i/o circuit type* function 1 vss ? gnd pin 2c ? power stabilization capacitance pin 3 p24 b general-purpose i/o port a04 bit 4 of external address bus output pin. enabled when external bus is effective. sot1 multi function serial 1 serial data output pin 4 p25 b general-purpose i/o port. enabled in single-chip mode. a05 bit 5 of external address bus output pin. enabled when external bus is effective. sck1 multi function serial 1 clock i/o pin 5 p26 b general-purpose i/o port. enabled in single-chip mode. a06 bit 6 of external address bus output pin. enabled when external bus is effective. sin2 multi function serial 2 serial data input pin 6 p27 b general-purpose i/o port. enabled in single-chip mode. a07 bit 7 of external address bus output pin. enabled when external bus is effective. sot2 multi function serial 2 serial data output pin 7 p30 b general-purpose i/o port. enabled in single-chip mode. a08 bit 8 of external address bus output pin. enabled when external bus is effective. sck2 multi function serial 2 clock i/o pin 8 p31 b general-purpose i/o port. enabled in single-chip mode. a09 bit 9 of external address bus output pin. enabled when external bus is effective. ain0 up down counter input pin tot0-2 reload timer output pin 9 p32 b general-purpose i/o port. enabled in single-chip mode. a10 bit 10 of external add ress bus output pin. enabled when external bus is effective. bin0 up down counter input pin tot1-2 reload timer output pin
mb91345 series 6 (continued) pin no. pin name i/o circuit type* function 10 p33 b general-purpose i/o port. enabled in single-chip mode. a11 bit 11 of external add ress bus output pin. enabled when external bus is effective. zin0 up down counter input pin tot2-2 reload timer output pin 11 p34 b general-purpose i/o port. enabled in single-chip mode. a12 bit 12 of external address bus output pin. enabled when external bus is effective. ain2 up down counter input pin 12 p35 b general-purpose i/o port. enabled in single-chip mode. a13 bit 13 of external add ress bus output pin. enabled when external bus is effective. bin2 up down counter input pin ic4 input capture icu 4 data sample input pin 13 p36 b general-purpose i/o port. enabled in single-chip mode. a14 bit 14 of external add ress bus output pin. enabled when external bus is effective. zin2 up down counter input pin ic5 input capture icu 5 data sample input pin 14 p37 b general-purpose i/o port. enabled in single-chip mode. a15 bit 15 of external address bus output pin. enabled when external bus is effective. frck1 16-bit free-run timer input pin 15 p40 b general-purpose i/o port a16 bit 16 of external add ress bus output pin. enabled when external bus is effective. ppg9 ppg output pin int16 external interrupt request 16 input pin 16 p41 b general-purpose i/o port a17 bit 17 of external address bus output pin. enabled when external bus is effective. ppgb ppg output pin int17 external interrupt request 17 input pin
mb91345 series 7 (continued) pin no. pin name i/o circuit type* function 17 p42 b general-purpose i/o port a18 bit 18 of external address bus output pin. enabled when external bus is effective. ppgd ppg output pin int18 external interrupt request 18 input pin 18 p43 b general-purpose i/o port a19 bit 19 of external add ress bus output pin. enabled when external bus is effective. ppgf ppg output pin int19 external interrupt request 19 input pin 19 p44 b general-purpose i/o port a20 bit 20 of external add ress bus output pin. enabled when external bus is effective. ic0 input capture icu0 data sample input pin int20 external interrupt request 20 input pin 20 p45 b general-purpose i/o port a21 bit 21 of external add ress bus output pin. enabled when external bus is effective. ic1 input capture icu1 data sample input pin int21 external interrupt request 21 input pin sin10 multi function serial 10 serial data input pin 21 p46 b general-purpose i/o port a22 bit 22 of external address bus output pin. enabled when external bus is effective. ic2 input capture icu2 data sample input pin int22 external interrupt request 22 input pin sot10 multi function serial 10 serial data output pin 22 p47 b general-purpose i/o port a23 bit 23 of external add ress bus output pin. enabled when external bus is effective. ic3 input capture icu3 data sample input pin int23 external interrupt request 10 input pin sck10 multi function serial 10 clock i/o pin
mb91345 series 8 (continued) pin no. pin name i/o circuit type* function 23 vss ? gnd pin 24 x1 a main clock i/o pin 25 x0 a main clock input pin 26 vcc ? power supply input pin (3.3 v) 27 pd0 e general-purpose i/o port an0 a/d converter analog input pin ain1 up down counter input pin 28 pd1 e general-purpose i/o port an1 a/d converter analog input pin bin1 up down counter input pin 29 pd2 e general-purpose i/o port an2 a/d converter analog input pin zin1 up down counter input pin 30 pd3 e general-purpose i/o port an3 a/d converter analog input pin ain3 up down counter input pin 31 pd4 e general-purpose i/o port an4 a/d converter analog input pin bin3 up down counter input pin 32 pd5 e general-purpose i/o port an5 a/d converter analog input pin zin3 up down counter input pin ppg0 ppg output pin 33 pd6 e general-purpose i/o port an6 a/d converter analog input pin ppg2 ppg output pin 34 pd7 e general-purpose i/o port an7 a/d converter analog input pin ppg4 ppg output pin
mb91345 series 9 (continued) pin no. pin name i/o circuit type* function 35 avcc ? a/d converter analog power supply input pin 36 avrh ? a/d converter standard voltage input pin be sure to turn on/off this power supply when potential of avrh or more is applied to avcc. 37 avrl ? a/d converter standard low voltage input pin 38 avss ? a/d converter analog gnd pin 39 pe0 e general-purpose i/o port an8 a/d converter analog input pin int0 external interrupt request 0 input pin ppg6 ppg output pin 40 pe1 e general-purpose i/o port an9 a/d converter analog input pin int1 external interrupt request 1 input pin ppg8 ppg output pin 41 pe2 e general-purpose i/o port an10 a/d converter analog input pin int2 external interrupt request 2 input pin ppga ppg output pin 42 pe3 e general-purpose i/o port an11 a/d converter analog input pin int3 external interrupt request 3 input pin ppgc ppg output pin 43 pe4 e general-purpose i/o port an12 a/d converter analog input pin int4 external interrupt request 4 input pin ppge ppg output pin 44 pe5 e general-purpose i/o port an13 a/d converter analog input pin int5 external interrupt request 5 input pin sin8 multi function serial 8 serial data input pin
mb91345 series 10 (continued) pin no. pin name i/o circuit type* function 45 pe6 e general-purpose i/o port an14 a/d converter analog input pin int6 external interrupt request 6 input pin sot8 multi function serial 8 serial data output pin 46 pe7 e general-purpose i/o port an15 a/d converter analog input pin int7 external interrupt request 7 input pin sck8 multi function serial 8 clock i/o pin 47 pc0 c general-purpose i/o port frck0 16-bit free-run timer input pin sin9 multi function serial 9 serial data input pin 48 pc1 c general-purpose i/o port ic6 input capture icu6 data sample input pin sot9 multi function serial 9 serial data output pin 49 pc2 c general-purpose i/o port ic7 input capture icu7 data sample input pin sck9 multi function serial 9 clock i/o pin 50 vss ? gnd pin 51 vcc ? power supply input pin (3.3 v) 52 iclk h development tool clock pin 53 icd0 k development tool data pin 54 icd1 k development tool data pin 55 icd2 k development tool data pin 56 icd3 k development tool data pin 57 ics0 j development tool status pin 58 ics1 j development tool status pin 59 ics2 j development tool status pin 60 ibreak i development tool break pin 61 trst g development tool reset pin 62 init g initial reset pin
mb91345 series 11 (continued) pin no. pin name i/o circuit type* function 63 md0 f mode input pin 64 md1 f mode input pin 65 md2 f mode input pin 66 p50 c general-purpose i/o port cs0 external chip select 0. enabled when external bus is effective. ppg1 ppg output pin 67 p51 c general-purpose i/o port cs1 external chip select pin. enabled when external bus is effective. ppg3 ppg output pin 68 p52 c general-purpose i/o port cs2 external chip select pin. enabled when external bus is effective. ppg5 ppg output pin 69 p53 c general-purpose i/o port cs3 external chip select pin. enabled when external bus is effective. ppg7 ppg output pin 70 p54 c general-purpose i/o port as external address strobe output pin. enabled when external bus is effective. rt4 output compare ocu4 waveform output pin 71 p55 c general-purpose i/o port rd external read strobe output pin. enabled when external bus is effective. rt5 output compare ocu5 waveform output pin 72 p56 d general-purpose i/o port wr0 external data bus upper 8-bit write strobe output pin. when external bus is effective, hi gh 8 bits of data during 16-bit access or 8 bits of data during 8- bit access is used as write strobe. rt6 output compare ocu6 waveform output pin
mb91345 series 12 (continued) pin no. pin name i/o circuit type* function 73 p57 d general-purpose i/o port wr1 external data bus lower 8-bit write strobe output pin. enabled when external bus is effective and external bus 16-bit mode is selected. rt7 output compare ocu7 waveform output pin 74 p60 c general-purpose i/o port rt0 output compare ocu0 waveform output pin 75 vss ? gnd pin 76 vcc ? power supply input pin (3.3 v) 77 p61 c general-purpose i/o port rt1 output compare ocu1 waveform output pin pwc0 pwc input pin adtrg0-2 a/d converter trigger input pin 78 p62 c general-purpose i/o port rdy external ready input pin. enabled when both external bus and bus request are effective. rt2 output compare ocu2 waveform output pin adtrg1-2 a/d converter trigger input pin 79 p63 c general-purpose i/o port sysclk external clock output pin. enabled when external bus is effective. rt3 output compare ocu3 waveform output pin 80 p00 c general-purpose i/o port d00 bit 0 of external address/data bus i/o pin. enabled when external bus is effective. sin3 multi function serial 3 serial data input pin int8 external interrupt request 8 input pin 81 p01 c general-purpose i/o port d01 bit 1 of external address/data bus i/o pin. enabled when external bus is effective. sot3 multi function serial 3 serial data output pin int9 external interrupt request 9 input pin
mb91345 series 13 (continued) pin no. pin name i/o circuit type* function 82 p02 c general-purpose i/o port d02 bit 2 of external address/data bus i/o pin. enabled when external bus is effective. sck3 multi function serial 3 clock i/o pin int10 external interrupt request 10 input pin 83 p03 c general-purpose i/o port d03 bit 3 of external address/data bus i/o pin. enabled when external bus is effective. sin4 multi function serial 4 serial data input pin int11 external interrupt request 11 input pin 84 p04 c general-purpose i/o port d04 bit 4 of external address/data bus i/o pin. enabled when external bus is effective. sot4 multi function serial 4 serial data output pin int12 external interrupt request 12 input pin 85 p05 c general-purpose i/o port d05 bit 5 of external address/data bus i/o pin. enabled when external bus is effective. sck4 multi function serial 4 clock i/o pin int13 external interrupt request 13 input pin 86 p06 c general-purpose i/o port d06 bit 6 of external address/data bus i/o pin. enabled when external bus is effective. sin5 multi function serial 5 serial data input pin int14 external interrupt request 14 input pin 87 p07 c general-purpose i/o port d07 bit 7 of external address/data bus i/o pin. enabled when external bus is effective. sot5 multi function serial 5 serial data output pin int15 external interrupt request 12 input pin 88 p10 c general-purpose i/o port d08 bit 8 of external address/data bus i/o pin. enabled when external bus is effective. sck5 multi function serial 5 clock i/o pin tin0 reload timer event input pin
mb91345 series 14 (continued) pin no. pin name i/o circuit type* function 89 p11 c general-purpose i/o port d09 bit 9 of external address/data bus i/o pin. enabled when external bus is effective. sin6 multi function serial 6 serial data input pin tot0 reload timer output pin 90 p12 c general-purpose i/o port d10 bit 10 of external address/data bus i/o pin. enabled when external bus is effective. sot6 multi function serial 6 serial data output pin tin1 reload timer event input pin 91 p13 c general-purpose i/o port d11 bit 11 of external address/data bus i/o pin. enabled when external bus is effective. sck6 multi function serial 6 clock i/o pin tot1 reload timer output pin 92 p14 c general-purpose i/o port d12 bit 12 of external address/data bus i/o pin. enabled when external bus is effective. sin7 multi function serial 7 serial data input pin tin2 reload timer event input pin 93 p15 c general-purpose i/o port d13 bit 13 of external address/data bus i/o pin. enabled when external bus is effective. sot7 multi function serial 7 serial data output pin tot2 reload timer output pin 94 p16 c general-purpose i/o port d14 bit 14 of external address/data bus i/o pin. enabled when external bus is effective. sck7 multi function serial 7 clock i/o pin adtrg1 a/d converter trigger input pin 95 p17 c general-purpose i/o port d15 bit 15 of external address/data bus i/o pin. enabled when external bus is effective. adtrg0 a/d converter trigger input pin
mb91345 series 15 (continued) * : for the i/o circuit type, refer to ? i/o circuit type?. pin no. pin name i/o circuit type* function 96 p20 c general-purpose i/o port a00 bit 0 of external address bus output pin. enabled when external bus is effective. sin0 multi function serial 0 serial data input pin 97 p21 c general-purpose i/o port a01 bit 1 of external address bus output pin. enabled when external bus is effective. sot0 multi function serial 0 serial data output pin 98 p22 c general-purpose i/o port a02 bit 2 of external address bus output pin. enabled when external bus is effective. sck0 multi function serial 0 clock i/o pin 99 p23 c general-purpose i/o port a03 bit 3 of external address bus output pin. enabled when external bus is effective. sin1 multi function serial 1 serial data input pin 100 vcc ? power supply input pin (3.3 v)
mb91345 series 16 i/o circuit type (continued) classification circuit type remarks a oscillation circuit feedback resistor x0 : 1 m ? b cmos level output i oh = 4 ma with open drain output control cmos level hysteresis input v ih = 0.7 v cc with standby control 5v tolerance c cmos level output i oh = 4 ma with open drain output control cmos level hysteresis input v ih = 0.8 v cc with standby control with pull-up resistor (33 k ? ) x1 x0 clock input standby control p-ch n-ch standby control open drain control digital output digital input p-ch p-ch n-ch standby control open drain control digital output digital input
mb91345 series 17 (continued) classification circuit type remarks d cmos level output i oh = 4 ma cmos level hysteresis input v ih = 0.8 v cc standby control provided without pull-up resistor e cmos level output i oh = 4 ma with open drain output control cmos level hysteresis input v ih = 0.8 v cc with standby control with analog input switch with pull-up resistor (33 k ? ) f cmos level input without standby control p-ch n-ch standby control digital output digital input digital output p-ch p-ch n-ch standby control open drain control digital output digital input analog input con- trol p-ch n-ch digital input
mb91345 series 18 (continued) classification circuit type remarks g cmos hysteresis input with pull-up resistor h cmos level output i cmos hysteresis input with pull-down resistor without standby control j cmos level output cmos level hysteresis input without standby control p-ch p-ch n-ch digital input p-ch n-ch digital output digital output p-ch n-ch n-ch digital input p-ch n-ch digital input digital output digital output
mb91345 series 19 (continued) classification circuit type remarks k cmos level output cmos level hysteresis input without standby control with pull-down resistor p-ch n-ch n-ch digital input digital output digital output
mb91345 series 20 handling devices ? preventing latch-up latch-up may occur in a coms ic if a voltage greater than vcc pin, or less th an vss pin is applied to input and output pins, or if an above-rating voltage is applie d between vcc pin and vss pin. if the latch-up occurs, the significantly increases the power supply current and may cause thermal destruction of an element. thus, when you use a cmos ic, be very carefu l not to exceed maximum voltage rating. ? treatment of unused input pins do not leave an unused input pin open, since it may cause a malfunction. thus, use pull- up or pull-down resistor. ? about power supply pins if there are multiple vcc pin or vss pi n, from the point of view of device design, pins to be of the same level are connected the inside of the device to prevent such malfunctioning as latc h-up. be sure to connect all of them to the power supply and ground externally for reducing unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of groun d level, and observe the total output current standard. in addition, consid- eration should be given to connecting vcc/vss of this device with as low an impedance as possible from the current supply source. also, we recommend connecting a ceramic capacitor of about 0.1 f as a bypass capacitor between vcc and vss near this device. ? about crystal oscillator circuit noise near the x0 and x1 pins can cause this device to malfunction. design the pc board such that x0 and x1 pins, crystal oscillator (or ceramic oscillator) , and bypa ss capacitor to the ground are placed as near one another as possible. it is strongly recommended to design the pc board artwork with the x0/x1 pins surrounded by a ground plane, as it expects stable operations. please ask the crystal maker to evaluate the oscillatio nal characteristics of the crystal and this device. ? about mode pins (md0 to md2) these pins should be connected directly to vcc or vs s pins. to prevent the device erroneously switching to test mode due to noise, design the pc board such that the distance bet ween the mode pins and vcc or vss pins is as short as possible a nd the connection impedance is low. ? about operation at power-on be sure to set initialized reset (init) with init pin immediately after power-on. immediately after turning on the power, be sure to continue connecting the lo w level input to the init pin for the stabilization wait time required for oscillator circuit, to secure the stabilization wait time of the oscillator and regulator (for init via the init pin, the oscillation stabilization wait time setting is initialized to the minimum value) . ? about oscillation input at power on when turning on the power, be sure that clock input is maintained until the device is released from the oscillation stabilization wait state. ? note on power-on/off sequences when turning on the power, the output pin may be indete rminate until the internal power supply stabilizes.
mb91345 series 21 ? note when using external clock in principle, when using external clock, supply a cloc k to the x0 pin and an opposite-phase clock signal to the x1 pin simultaneously. however in this case, the stop mode (oscillator stop mode) must not be used, because the x1 pin stops with the ?h? output in the stop mode. at 12.5 mhz or less, the device can be used with the clock signal supplied only to the x0 pin. note : the x1 pin must be designed to have a delay within 15 ns, at 10 mhz, from the signal to the x0 pin. ? about c pin mb91345 series has an internal regulator. a bus condenser of 4.7 f or above should be connected to the c pin for the regulator. ? about avcc pin mb91345 series has an internal a/d converter. a c ondenser of approximately 0.1 f should be connected between the avcc pin and avss pin. ? treatment of nc pin and open pin the nc and open pins should always be open. x0 x1 [the stop mode (oscillation stop mode) cannot be used.] mb91345 series using an external clock (normal method) x0 x1 mb91345 series open using an external (enabled at 12.5 mhz or lower) 4.7 f vss c avcc 0.1 f avss
mb91345 series 22 ? note when not using emulator if evaluation mcu on user system is operated without emulator, each input pin on evaluation mcu connected to the emulator interface on the user system should be handled, as described in the following table. note that the switch circuit or other function may be r equired on user system when designing the mcu. emulator interface pin treatment evaluation mcu pin name pin processing trst connect to the reset output circuit on the user system. init connect to the reset output circuit on the user system. others open.
mb91345 series 23 restrictions ? common in the series clock control block take the oscillation stabilization wait time during low level input to init pin. bit search module the bit search data register for 0-detection (bsd0) , a nd bit search data register for 1-detection (bsd1) , and bit search data register for change point detection (bsdc) are only word-accessible. i/o port ports are accessed only in bytes. low power consumption mode to enter the standby mode, use the sy nchronous standby mode (set with th e syncs bit as bit8 in tbcr, or timebase counter control register) and be sure to use the following sequence : please do not do the following wh en the monitor debugger is used ? setting of the break point to the above instructions. ? execution of the single-stepping for the above instructions. (ldi #value_of_standby, r0) (ldi #_stcr, r12) stb r0, @r12 // set stop/sleep bit ldub @r12, r0 // must read stcr ldub @r12, r0 // after reading, go into standby mode nop // must insert nop *5 nop nop nop nop
mb91345 series 24 notes on the ps register as the ps register is processed by some instructi ons in advance, exception handling below may cause the interrupt handling routine to break when the debugger is used or the displa y contents of flags in the ps register to be updated. in either case, the operations before a nd after an eit are performed as specified as the device is designed such that the recovery from t he eit is followed by correct re-processing. the instruction just before the div0u/div0s instructio n may cause the following operation, if a user interrupt or nmi occurs, single-stepping is performed or a br eak is caused by a data event or emulator menu : (1) the d0 and d1 flags are updated in advance. (2) an eit handling routine (user interrupt, nmi, or emulator) is executed. (3) upon returning from the eit, the div0u/div0s in struction is executed and the d0 and d1 flags are updated to the same values as shown in (1) . if the orccr/stilm/mov ri and ps instructions are ex ecuted to enable interruptions when a user interrupt or nmi trigger even has occurred, the following operations are performed. (1) the ps register is updated in advance. (2) an eit handling routine (user interrupt, nmi, or emulator) is executed. (3) upon returning from the eit, the instructions shown above are executed and the ps register is updated to the same value as shown in (1) . about watchdog timer mb91345 series has an internal function called ?watchdog timer?. this function monitors a program to perform the reset defer operation within a certain period of ti me. the watchdog timer resets the cpu if the program runs out of controls and the reset defer operation is not executed. thus, once enabled, the watchdog timer will be up and running until it resets the cpu. however, with one exception, the watchdog timer automatically defers a reset timing under the condition in which the cpu stops program execution. refer to the section describing the watchdog timer functions for the exceptio nal condition. if the system runs out of control and develops the above condition, a watchdog reset may not be generated. in that case, please reset (init) from external init terminal. note on using the a/d converter mb91345 series has an internal a/d converter. the avcc pin should not be supplied with higher voltage than vcc pin. software reset in synchronous mode when using the software reset in the synchronous mo de, the following two conditions should be satisfied before setting ?0? to the srst bit in stcr (standby control register) . ? set the interrupt enable flag (i-f lag) to interrupt disable (i-flag = 0) . ? do not use nmi. ? debug control when using ice single-stepping of the reti instruction if an interrupt occurs frequently during single stepping, on ly the relevant interrupt processing routine is executed repeatedly after single-stepping reti. this will prevent the main routine and low-interrupt-level programs from being executed. do not single-step the reti instruction for escape. when the debugging of the relevant interrupt routine no longer requires, perfor m debugging with that interrupt disabled. about operand break do not apply a data event break to access to the area containing the address of a stack pointer.
mb91345 series 25 execution of an unused area of flash memory accidently if an unused area (data at 0xffff) of flash memory is executed in an instruction, no break can be accepted. to avoid this, it is recommended to us e the code event address mask feature of the debugger to break at instruction access to the unused area. interrupt handler for nmi request (tool) add the following program to the interrupt handler to prevent the device from ma lfunctioning when the source flag is set accidentlly with no ice connected, for example, due to nois e to the dsu pin, wh ich is to be set only at the break request of the ice. can be used normally with this program added. add place : next interrupt handler interrupt source : nmi request (tool) interrupt number : 13 (decimal) , 0d (hexadecimal) offset : 3c8h tbr default address : 000fffc8 h add program stm (r0, r1) ldi #0b00h, r0 ; 0b00h is the address of dsu break source register ldi #0, r1 stb r1, @r0 ; clear the break source register ldm (r0, r1) reti
mb91345 series 26 block diagram 3 2 3 2 3 2 16 3 2 d15 ~ d00 a2 3 ~ a00 rd, wr1, wr0 rdy s y s clk int2 3 ~ int0 an7 ~ an0 adtrg0, adtrg0-2 port ppgf ~ ppgf0 c s3 ~ c s 0 x0, x1 md2 ~ md0 init s in10 ~ s in0 s ot10 ~ s ot0 s ck10 ~ s ck0 avrh, avcc av ss /avrl an15 ~ an 8 adtrg1, adtrg1-2 ain 3 ~ ain0, bin 3 ~ bin0, zin 3 ~ zin0 ic 3 ~ ic0 rt 3 ~ rt0 frck0 tot2 ~ tot0 ic7 ~ ic4 frck1 rt7 ~ rt4 tin2 ~ tin0 bit search ram 24 kbytes (data) flash 512 kbytes ram 8 kbytes clock control interrupt controller 24 channels external interrupt 11 channels multi function serial interface. (including 2 channels with built-in fifo) 8 channels 1 unit 10-bit a/d converter 8 channels 1 unit 10-bit a/d converter 2 channels 8/16-bit up down counter 16 channels 8/16-bit ppg bus converter 32 ? 16 adapter dmac 5 channels external memory i/f port 3 channels 16-bit reload timer 16-bit free-run timer 4 channels 16-bit input capture 4 channels 16-bit output compare 32-bit free-run timer 4 channels 32-bit input capture 4 channels 32-bit output compare fr60 lite cpu core operating macro for absolute value
mb91345 series 27 cpu and control unit the fr family cpu is a line of high-performance core s based on a risc architecture while incorporating advanced instructions for embedded controller applications. 1. features risc architecture adopted. basic instructions : executed at 1 instruction per cycle 32-bit architecture general purpose registers : 32 bit 16 4g bytes of linear memory space multiplier integrated. 32-bit 32-bit multiplication : 5 cycles. 16-bit 16-bit multiplication : 3 cycles enhanced interrupt servicing. high-speed response (6 cycles) . multi-level interrupts support. level mask feature (16 levels) enhanced i/o manipulation instructions. memory-to-memory transfer instructions bit manipulation instructions high code efficiency. basic instruction word length : 16-bit low-power consumption. sleep mode / stop mode gear function
mb91345 series 28 2. internal architecture the fr-family cpu has a harvard architecture in whic h the instruction bus and data buses are separated. the 32-bit 16-bit bus converter is connected to a 32-bit bus (f-bus) , providing an interface between the cpu and peripheral resources. the harvard princeton bus converter is connected to both of the i-bus and d-bus, providing an interface between the cpu and the bus controller. fr cpu data ram 32-bit 16-bit bus converter harvard princeton bus converter d-bus i-bus d address i address external address external data d data address data 16 16 24 32 32 32 32 32 32 i data r-bus f-bus peripherals resource internal i/o bus controller
mb91345 series 29 3. programming model basic programming model r0 r1 r12 r13 r14 r15 pc ps ? ilm ? scr ccr tbr rp ssp usp mdh mdl ac fp sp xxxx xxxx h xxxx xxxx h 0000 0000 h 32-bit initial value general purpose registers program counter program status table base register return pointer system stack pointer user stack pointer multiply and divide result register
mb91345 series 30 4. register general purpose registers registers r0 to r15 are general purpose registers. the registers are used as the accumulator and memory access pointers for cpu operations. of these 16 registers, the registers listed below are int ended for special applications, for which some instructions are enhanced. r13 : virtual accumulator r14 : frame pointer r15 : stack pointer the initial values of r0 to r14 after a rese t are indeterminate. r15 is initialized to 00000000 h (ssp value) . ? ps (program status) this register holds the program status and is divided into the ilm, scr, and ccr. all of undefined bits are reserved bits. reading these bits always returns ?0?. writing to them has no effect. ? ccr (condition code register) s : stack flag. cleared to ?0? at a reset. r0 r1 r12 r13 r14 r15 ac fp sp xxxx xxxx h xxxx xxxx h 0000 0000 h 32 bit initial value ps bit31 bit20 bit16 ilm scr ccr bit10 bit7 bit8 bit0 ? ? initial value - - 00xxxx b bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ?? sinzvc
mb91345 series 31 ? scr (system condition code register) flag for step dividing stores intermediate data for stepwise multiplication operations. step trace trap flag a flag specifying whether the step trac e trap function is enabled or not. emulator uses step trace trap function. the function cannot be used by the user program when using the emulator. ? ilm (interrupt level mask register) this register stores the interrupt level mask value. th e value in the ilm register is used as the level mask. initialized to ?15? (01111 b ) by a reset. ? pc (program counter) the program counter contains the address of the instruction currently being executed. the initial value after a reset is indeterminate. ? tbr (table base register) the table base register contains the start address of the vector table used for servicing eit events. the initial value after a reset is 000ffc00 h . i : interrupt enable flag. cleared to ?0? at a reset. n : negative flag. initial stat e at a reset is unspecified. z : zero flag. initial state at a reset is unspecified. v : overflow flag. initial state at a reset is unspecified. c : carry flag. initial state at a reset is unspecified. initial value xx0 b bit10 bit9 bit8 d1 d0 t initial value 01111 b bit20 bit19 bit18 bit17 bit16 ilm4 ilm3 ilm2 ilm1 ilm0 initial value xxxxxxxx h bit31 bit0 initial value 000ffc00 h bit31 bit0
mb91345 series 32 ? rp (return pointer) the return pointer contains the address to which to return from a subroutine. when the call instruction is executed, the va lue in the pc is transferred to the rp. when the ret instruction is executed, the va lue in the rp is transferred to the pc. the initial value after a reset is indeterminate. ? ssp (system stack pointer) the ssp is the system stack pointer and functions as r15 when the s flag is ?0?. the ssp can be explicitly specified. the ssp is also used as the stack point er that specifies the stack for sa ving the ps and pc when an eit event occurs. the initial value after a reset is 00000000 h . ? usp (user stack pointer) the usp is the user stack pointer and functions as r15 when the s flag is ?1?. the usp can be explicitly specified. the initial value after a reset is indeterminate. this pointer cannot be used by the reti instruction. ? mdh, mdl (multiply and divide register) these registers hold the results of a multiplicat ion or division. each of them is 32-bit long. the initial value after a reset is indeterminate. initial value xxxxxxxx h bit31 bit0 initial value 00000000 h bit31 bit0 initial value xxxxxxxx h bit31 bit0 multiplication and division result register bit31 bit0 mdh mdl
mb91345 series 33 mode setting in the fr family, operation mode is set by the mode setting pins (md2, md1, md0) and the mode register (modr) . 1. mode pins they are three pins of md2, md 1 and md0, and specify the conten ts of the mode vector fetch. note : in the fr family, external mode vect or fetch by multiplex bus is not supported. 2. mode register (modr) the data that are written in the mode register by mode vector fetch is called mode data. after the mode register (modr) is set, it operat es in the operation mode set by this register. the mode register is set by all reset source. and m ode data is not written in by the user program. note : conventionally, the address (0000 07ff h ) of the mode register for the fr family holds nothing. details of the mode register [bit7 to bit3] reserved bits be sure to set these bits to ?00000 b ?. setting the bits to any value other than ?00000 b ? may result in an unpredictable operation . [bit2] roma (internal rom enable bit) this bit sets to make internal f-bus ram and f-bus rom areas valid or not. mode pins mode name reset vector access area md2 md1 md0 0 0 0 internal rom mode vector internal roma function remarks 0 external rom mode embedded f-bus ram becomes valid, and internal rom area (50000 h to 100000 h ) becomes external area. 1 internal rom mode embedded f-bus ram and f-bus rom become valid. modr initial value 0007fd h xxxxxxxx b bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 0 0 0 roma wth1 wth0 operation mode setting bits
mb91345 series 34 [bit1, bit0] wth1, wth0 (b us width specifying bits) these bits specify bus widths for the external bus mode. in case of the external bus mode, this value is set in the dbw0 bit of acr0 (cs0 area) . wth1 wth0 function remarks 0 0 8-bit bus width external bus mode 0 1 16-bit bus width external bus mode 10 ? setting disabled 1 1 single chip mode single chip mode
mb91345 series 35 memory space 1. memory space the fr family has 4 gbytes of logical address space (2 32 addresses) linearly accessible to the cpu . ? direct addressing areas the following address space ar eas are used as i/o areas. these areas are called direct addressing areas, in wh ich the address of an operand can be specified directly during an instruction. the direct area varies depending on the size of data to be accessed as follows : byte data access : 000 h to 0ff h half word data access : 000 h to 1ff h word data access : 000 h to 3ff h 2. memory map (mb91f345b/f346b) i/o i/o 0000 0000 h 0000 0400 h 0001 0000 h 0003 e000 h 0004 0000 h 0004 6000 h 0005 0000 h 0008 0000 h 0010 0000 h 0020 0000 h ffff ffff h i/o i/o single chip mode internal rom external bus mode direct addressing area refer to ?3. i/o map? access prohibited internal ram 8 kbytes (data/instruction) internal ram 24 kbytes (data) internal flash* 512 kbytes access prohibited access prohibited access prohibited internal ram 8 kbytes (data/instruction) internal ram 24 kbytes (data) internal flash* 512 kbytes access prohibited access prohibited external area external area * : internal flash area of mb91f346b is 0008 0000 h to 0018 0000 h (1 mbyte.)
mb91345 series 36 i/o map the following table shows the correspondence between the memory space area and each register of the pe- ripheral resource. [how to read the table] note : initial values of register bits are represented as follows : access is barred with an undef ined data access attribute. ?1? : initial value is ?1?. ?0? : initial value is ?0?. ?x? : initial value is ?indeterminate?. ? ? ? : no physical register at this location address register block + 0 + 1 + 2 + 3 000000 h pdr0 [r/w] b xxxxxxxx pdr1 [r/w] b xxxxxxxx pdr2 [r/w] b xxxxxxxx pdr3 [r/w] b xxxxxxxx t-unit port data register initial value after a reset register name (first-column register at address 4n; second-column register at address 4n + 1...) read/write attribute, access unit (b : byte, h : half word, w : word) location of left-most register (when using word access, the register in column 1 is in the msb side of the data.)
mb91345 series 37 (continued) address register block 0123 000000 h pdr0 [r/w] b, h xxxxxxxx pdr1 [r/w] b, h xxxxxxxx pdr2 [r/w] b, h xxxxxxxx pdr3 [r/w] b, h xxxxxxxx port data registers 000004 h pdr4 [r/w] b, h xxxxxxxx pdr5 [r/w] b, h xxxxxxxx pdr6 [r/w] b, h ----xxxx ? 000008 h ? 00000c h pdrc [r/w] b, h -----xxx pdrd [r/w] b, h xxxxxxxx pdre [r/w] b, h xxxxxxxx ? 000010 h to 00001c h ? reserved 000020 h ? aderh0 [r/w] 11111111 a/d converter 0 000024 h adcs01 [r/w] 00000000 adcs00 [r, r/w] 00000000 adcr0 [r] ------xx xxxxxxxx 000028 h adct0 [r/w] 00010000 00101100 adsch0 [r/w] 0---0000 adech0 [r/w] ----0000 00002c h adcr0m [r] ------xx xxxxxxxx adcr1m [r] ------xx xxxxxxxx ad mirror data register 000030 h ? aderh1 [r/w] 11111111 a/d converter 1 000034 h adcs11 [r/w] 00000000 adcs10 [r, r/w] 00000000 adcr1 [r] ------xx xxxxxxxx 000038 h adct1 [r/w] 00010000 00101100 adsch1 [r/w] 0----000 adech1 [r/w] -----000 00003c h ? reserved 000040 h eirr0 [r/w] 00000000 enir0 [r/w] 00000000 elvr0 [r/w] 00000000 00000000 external interrupt int 0 to int7 000044 h dicr [r/w] 00000000 hrcl [r, r/w] 0--11111 ? dly / i-unit 000048 h tmrlr0 [w] xxxxxxxx xxxxxxxx tmr0 [r] xxxxxxxx xxxxxxxx reload timer 0 00004c h ? tmcsr0 [r, rw] 00000000 00000000 000050 h tmrlr1 [w] xxxxxxxx xxxxxxxx tmr1 [r] xxxxxxxx xxxxxxxx reload timer 1 000054 h ? tmcsr1 [r, rw] 00000000 00000000
mb91345 series 38 (continued) address register block 0123 000058 h tmrlr2 [w] xxxxxxxx xxxxxxxx tmr2 [r] xxxxxxxx xxxxxxxx reload timer 2 00005c h ? tmcsr2 [r, rw] 00000000 00000000 000060 h scr0/ibcr0 [r, r/w] * smr0 [w, r/w] * ssr0 [r, r/w] * escr0/ibsr0 [r/w] * multi function serial interface 0 fifo 0 000064 h rdr0/tdr0 [r/w] * bgr01 [r/w] * bgr00 [r/w] * 000068 h ismk0 [r/w] * ibsa [r/w] * fcr01 [r/w] * fcr00 [r/w] * 00006c h fbyte02 [r/w] * fbyte01 [r/w] * ? 000070 h scr1/ibcr1 [r, r/w] * smr1 [w, r/w] * ssr1 [r, r/w] * escr1/ibsr1 [r/w] * multi function serial interface 1 fifo 1 000074 h rdr1/tdr1 [r/w] * bgr11 [r/w] * bgr10 [r/w] * 000078 h ismk1 [r/w] * ibsa1 [r/w] * fcr11 [r/w] * fcr10 [r/w] * 00007c h fbyte12 [r/w] * fbyte11 [r/w] * ? 000080 h scr2/ibcr2 [r, r/w] * smr2 [w, r/w] * ssr2 [r, r/w] * escr2/ibsr2 [r/w] * multi function serial interface 2 000084 h rdr2/tdr2 [r/w] * bgr21 [r/w] * bgr20 [r/w] * 000088 h ismk2 [r/w] * ibsa2 [r/w] * ? 00008c h ? 000090 h scr3/ibcr3 [r, r/w] * smr3 [w, r/w] * ssr3 [r, r/w] * escr3/ibsr3 [r/w] * multi function serial interface 3 000094 h rdr3/tdr3 [r/w] * bgr31 [r/w] * bgr30 [r/w] * 000098 h ismk3 [r/w] * ibsa3 [r/w] * ? 00009c h ?
mb91345 series 39 (continued) address register block 0123 0000a0 h scr4/ibcr4 [r, r/w] * smr4 [w, r/w] * ssr4 [r, r/w] * escr4/ibsr4 [r/w] * multi function serial interface 4 0000a4 h rdr4/tdr4 [r/w] * bgr41 [r/w] * bgr40 [r/w] * 0000a8 h ismk4 [r/w] * ibsa4 [r/w] * ? 0000ac h ? 0000b0 h scr5/ibcr5 [r, r/w] * smr5 [w, r/w] * ssr5 [r, r/w] * escr5/ibsr5 [r/w] * multi function serial interface 5 0000b4 h rdr5/tdr5 [r/w] * bgr51 [r/w] * bgr50 [r/w] * 0000b8 h ismk5 [r/w] * ibsa5 [r/w] * ? 0000bc h ? 0000c0 h eirr1 [r/w] 00000000 enir1 [r/w] 00000000 elvr1 [r/w] 00000000 00000000 external interrupt int 8 to int15 0000c4 h eirr2 [r/w] 00000000 enir2 [r/w] 00000000 elvr2 [r/w] 00000000 00000000 external interrupt int 16 to int 23 0000c8 h to 0000cc h ? reserved 0000d0 h cpclrb/cpclr [r/w] h 11111111 11111111 tcdt [r/w] h 00000000 00000000 16-bit free run timer 0 0000d4 h tccsh [r/w] b 00000000 tccsl [r/w] b 01000000 ? 0000d8 h ? reserved 0000dc h ipcph0/ipcpl0 [r] xxxxxxxx xxxxxxxx ipcph1/ipcpl1 [r] xxxxxxxx xxxxxxxx 16-bit input capture 0000e0 h ipcph2/ipcpl2 [r] xxxxxxxx xxxxxxxx ipcph3/ipcpl3 [r] xxxxxxxx xxxxxxxx 0000e4 h icsh01 [r/w] ------00 icsl01 [r/w] 00000000 icsh23 [r/w] ------00 icsl23 [r/w] 00000000 0000e8 h occph0/occpl0 [r/w] xxxxxxxx xxxxxxxx occph1/occpl1 [r/w] xxxxxxxx xxxxxxxx output compare 0, 1 0000ec h occph2/occpl2 [r/w] xxxxxxxx xxxxxxxx occph3/occpl3 [r/w] xxxxxxxx xxxxxxxx output compare 2, 3 0000f0 h ocs01 [r/w] 11101100 00001100 ocs23 [r/w] 11101100 00001100 output compare 0 to 3 control
mb91345 series 40 (continued) address register block 0123 0000f4 h ocmod [r/w] b 00000000 ? output compare mode select 0000f8 h pwcsr0 [r/w, r] b, h, w 0000000x 00000000 pwcr0 [r] h, w 00000000 00000000 pwc 0000fc h ? pdivr0 [r/w] b, h, w xxxxx000 ? 000100 h prlh0 [r/w] b, h, w xxxxxxxx prll0 [r/w] b, h, w xxxxxxxx prlh1 [r/w] b, h, w xxxxxxxx prll1 [r/w] b, h, w xxxxxxxx ppg 0 to ppg f 000104 h prlh2 [r/w] b, h, w xxxxxxxx prll2 [r/w] b, h, w xxxxxxxx prlh3 [r/w] b, h, w xxxxxxxx prll3 [r/w] b, h, w xxxxxxxx 000108 h ppgc0 [r/w] b, h, w 0000000x ppgc1 [r/w] b, h, w 0000000x ppgc2 [r/w] b, h, w 0000000x ppgc3 [r/w] b, h, w 0000000x 00010c h prlh4 [r/w] b, h, w xxxxxxxx prll4 [r/w] b, h, w xxxxxxxx prlh5 [r/w] b, h, w xxxxxxxx prll5 [r/w] b, h, w xxxxxxxx 000110 h prlh6 [r/w] b, h, w xxxxxxxx prll6 [r/w] b, h, w xxxxxxxx prlh7 [r/w] b, h, w xxxxxxxx prll7 [r/w] b, h, w xxxxxxxx 000114 h ppgc4 [r/w] b, h, w 0000000x ppgc5 [r/w] b, h, w 0000000x ppgc6 [r/w] b, h, w 0000000x ppgc7 [r/w] b, h, w 0000000x 000118 h prlh8 [r/w] b, h, w xxxxxxxx prll8 [r/w] b, h, w xxxxxxxx prlh9 [r/w] b, h, w xxxxxxxx prll9 [r/w] b, h, w xxxxxxxx 00011c h prlha [r/w] b, h, w xxxxxxxx prlla [r/w] b, h, w xxxxxxxx prlhb [r/w] b, h, w xxxxxxxx prllb [r/w] b, h, w xxxxxxxx 000120 h ppgc8 [r/w] b, h, w 0000000x ppgc9 [r/w] b, h, w 0000000x ppgca [r/w] b, h, w 0000000x ppgcb [r/w] b, h, w 0000000x 000124 h prlhc [r/w] b, h, w xxxxxxxx prllc [r/w] b, h, w xxxxxxxx prlhd [r/w] b, h, w xxxxxxxx prlld [r/w] b, h, w xxxxxxxx 000128 h prlhe [r/w] b, h, w xxxxxxxx prlle [r/w] b, h, w xxxxxxxx prlhf [r/w] b, h, w xxxxxxxx prllf [r/w] b, h, w xxxxxxxx 00012c h ppgcc [r/w] b, h, w 0000000x ppgcd [r/w] b, h, w 0000000x ppgce [r/w] b, h, w 0000000x ppgcf [r/w] b, h, w 0000000x
mb91345 series 41 (continued) address register block 0123 000130 h ppgtrg [r/w] b, h, w 00000000 00000000 ? ppggatec [r/w] b xxxxxx00 ppg 0-f 000134 h ppgrevc [r/w] b, h, w 00000000 00000000 ? 000138 h to 00014c h ? reserved 000150 h cpclrb/cpclr [r/w] w 11111111 11111111 11111111 11111111 32 bit free run timer 0 000154 h tcdt [r/w] w 00000000 00000000 00000000 00000000 000158 h tccsh [r/w] b 00000000 tccsl [r/w] b 01000000 ? 32 bit input capture unit 4 to 7 00015c h ipcp4 [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000160 h ipcp5 [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000164 h ipcp6 [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000168 h ipcp7 [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00016c h ? ics45 [r/w] 00000000 ? ics67 [r/w] 00000000 000170 h occp4 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 32 bit output compare 4 to 7 000174 h occp5 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000178 h occp6 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00017c h occp7 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000180 h ocs45 [r/w] 11101100 00001100 ocs67 [r/w] 11101100 00001100 000184 h rcrh1 [w] b, h 00000000 rcrl0 [w] b, h 00000000 udcr1 [r] b, h 00000000 udcr0 [r] b, h 00000000 up/down counter 0, 1 000188 h ccrh0 [r/w] b, h 00000000 ccrl0 [r/w] b, h 00000000 ? csr0 [r/w] b 00000000 00018c h ccrh1 [r/w] b, h 00000000 ccrl1 [r/w] b, h 00000000 ? csr1 [r/w] b 00000000
mb91345 series 42 (continued) address register block 0123 000190 h ? reserved 000194 h rcrh3 [w] b, h 00000000 rcrl2 [w] b, h 00000000 udcr3 [r] b, h 00000000 udcr2 [r] b, h 00000000 up/down counter 2, 3 000198 h ccrh2 [r/w] b, h 00000000 ccrl2 [r/w] b, h 00000000 ? csr2 [r/w] b 00000000 00019c h ccrh3 [r/w] b, h 00000000 ccrl3 [r/w] b, h 00000000 ? csr3 [r/w] b 00000000 0001a0 h to 0001ac h ? reserved 0001b0 h scr6/ibcr6 [r, r/w] * smr6 [w, r/w] * ssr6 [r, r/w] * escr6/ibsr6 [r/w] * multi function serial interface 6 0001b4 h rdr6/tdr6 [r/w] * bgr61 [r/w] * bgr60 [r/w] * 0001b8 h ismk6 [r/w] * ibsa6 [r/w] * ? 0001bc h ? 0001c0 h scr7/ibcr7 [r, r/w] * smr7 [w, r/w] * ssr7 [r, r/w] * escr7/ibsr7 [r/w] * multi function serial interface 7 0001c4 h rdr7/tdr7 [r/w] * bgr71 [r/w] * bgr70 [r/w] * 0001c8 h ismk7 [r/w] * ibsa7 [r/w] * ? 0001cc h ? 0001d0 h scr8/ibcr8 [r, r/w] * smr8 [w, r/w] * ssr8 [r, r/w] * escr8/ibsr8 [r/w] * multi function serial interface 8 0001d4 h rdr8/tdr8 [r/w] * bgr81 [r/w] * bgr80 [r/w] * 0001d8 h ismk8 [r/w] * ibsa8 [r/w] * ? 0001dc h ?
mb91345 series 43 (continued) address register block 0123 0001e0 h scr9/ibcr9 [r, r/w] * smr9 [w, r/w] * ssr9 [r, r/w] * escr9/ibsr9 [r/w] * multi function serial interface 9 0001e4 h rdr9/tdr9 [r/w] * bgr91 [r/w] * bgr90 [r/w] * 0001e8 h ismk9 [r/w] * ibsa9 [r/w] * ? 0001ec h ? 0001f0 h scra/ibcra [r, r/w] * smra [w, r/w] * ssra [r, r/w] * escra/ibsra [r/w] * multi function serial interface 10 0001f4 h rdra/tdra [r/w] * bgra1 [r/w] * bgra0 [r/w] * 0001f8 h ismka [r/w] * ibsaa [r/w] * ? 0001fc h ? 000200 h dmaca0 [r/w] 00000000 00000000 00000000 00000000 dmac 000204 h dmacb0 [r/w] 00000000 00000000 00000000 00000000 000208 h dmaca1 [r/w] 00000000 00000000 00000000 00000000 00020c h dmacb1 [r/w] 00000000 00000000 00000000 00000000 000210 h dmaca2 [r/w] 00000000 00000000 00000000 00000000 000214 h dmacb2 [r/w] 00000000 00000000 00000000 00000000 000218 h dmaca3 [r/w] 00000000 00000000 00000000 00000000 00021c h dmacb3 [r/w] 00000000 00000000 00000000 00000000 000220 h dmaca4 [r/w] 00000000 00000000 00000000 00000000 000224 h dmacb4 [r/w] 00000000 00000000 00000000 00000000 000228 h to 00023c h ? reserved 000240 h dmacr [r/w] 0xx00000 xxxxxxxx xxxxxxxx xxxxxxxx dmac
mb91345 series 44 (continued) address register block 0123 000244 h to 0003bc h ? reserved 0003a0 h data_a [-/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx min/max/abs 0003a4 h data_b [-/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003a8 h min [r/w] 00000000 00000000 00000000 00000000 0003ac h max [r/w] 00000000 00000000 00000000 00000000 0003b0 h abs [r/w] 00000000 00000000 00000000 00000000 0003b4 h to 0003ec h ? reserved 0003f0 h bsd0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx bit search 0003f4 h bsd1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003f8 h bsdc [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003fc h bsrr [r] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000400 h ddr0 [r/w] b, h 00000000 ddr1 [r/w] b, h 00000000 ddr2 [r/w] b, h 00000000 ddr3 [r/w] b, h 00000000 data direction registers 000404 h ddr4 [r/w] b, h 00000000 ddr5 [r/w] b, h 00000000 ddr6 [r/w] b, h ----0000 ? 000408 h ? 00040c h ddrc [r/w] b, h -----000 ddrd [r/w] b, h 00000000 ddre [r/w] b, h 00000000 ? 000410 h ? 000414 h to 00041c h ? reserved
mb91345 series 45 (continued) address register block 0123 000420 h pfr0 [r/w] b, h 00000000 pfr1 [r/w] b, h 00000000 pfr2 [r/w] b, h 00000000 pfr3 [r/w] b, h 00000000 registers 000424 h pfr4 [r/w] b, h 00000000 pfr5 [r/w] b, h 00000000 pfr6 [r/w] b, h ----0000 ? 000428 h ? 00042c h pfrc [r/w] b, h -----000 pfrd [r/w] b, h 00000000 pfre [r/w] b, h 00000000 ? 000430 h ? 000434 h to 00043c h ? reserved 000440 h icr00 [r, r/w] ---11111 icr01 [r, r/w] ---11111 icr02 [r, r/w] ---11111 icr03 [r, r/w] ---11111 interrupt control unit 000444 h icr04 [r, r/w] ---11111 icr05 [r, r/w] ---11111 icr06 [r, r/w] ---11111 icr07 [r, r/w] ---11111 000448 h icr08 [r, r/w] ---11111 icr09 [r, r/w] ---11111 icr10 [r, r/w] ---11111 icr11 [r, r/w] ---11111 00044c h icr12 [r, r/w] ---11111 icr13 [r, r/w] ---11111 icr14 [r, r/w] ---11111 icr15 [r, r/w] ---11111 000450 h icr16 [r, r/w] ---11111 icr17 [r, r/w] ---11111 icr18 [r, r/w] ---11111 icr19 [r, r/w] ---11111 000454 h icr20 [r, r/w] ---11111 icr21 [r, r/w] ---11111 icr22 [r, r/w] ---11111 icr23 [r, r/w] ---11111 000458 h icr24 [r, r/w] ---11111 icr25 [r, r/w] ---11111 icr26 [r, r/w] ---11111 icr27 [r, r/w] ---11111 00045c h icr28 [r, r/w] ---11111 icr29 [r, r/w] ---11111 icr30 [r, r/w] ---11111 icr31 [r, r/w] ---11111 000460 h icr32 [r, r/w] ---11111 icr33 [r, r/w] ---11111 icr34 [r, r/w] ---11111 icr35 [r, r/w] ---11111 000464 h icr36 [r, r/w] ---11111 icr37 [r, r/w] ---11111 icr38 [r, r/w] ---11111 icr39 [r, r/w] ---11111 000468 h icr40 [r, r/w] ---11111 icr41 [r, r/w] ---11111 icr42 [r, r/w] ---11111 icr43 [r, r/w] ---11111 00046c h icr44 [r, r/w] ---11111 icr45 [r, r/w] ---11111 icr46 [r, r/w] ---11111 icr47 [r, r/w] ---11111 000470 h to 00047c h ? reserved
mb91345 series 46 (continued) address register block 0123 000480 h rsrr [r, r/w] 10000000 stcr [r/w] 00110011 tbcr [r/w] 00xxxx00 ctbr [w] xxxxxxxx clock control unit 000484 h clkr [r/w] 00000000 wpr [w] xxxxxxxx divr0 [r/w] 00000011 divr1 [r/w] 00000000 000488 h ? osccr [r/w] xxxxxxxx ? 00048c h ? reserved 000490 h oscr [r/w] 00000000 osct [r/w] xxxxxxxx ? stb. wait timer 000494 h to 0004fc h ? reserved 000500 h pcr0 [r/w] b, h 00000000 pcr1 [r/w] b, h 00000000 ? port pull-up control registers 000504 h ? pcr5 [r/w] b, h 00000000 pcr6 [r/w] b, h ----0000 ? 000508 h ? 00050c h pcrc [r/w] b, h -----000 pcrd [r/w] b, h 00000000 pcre [r/w] b, h 00000000 ? 000510 h ? 000514 h to 00051c h ? reserved 000520 h epfr0 [r/w] b, h 00000000 epfr1 [r/w] b, h 00000000 epfr2 [r/w] b, h 11111111 epfr3 [r/w] b, h 11111111 extra port function registers 000524 h epfr4 [r/w] b, h 11111111 epfr5 [r/w] b, h 11111111 epfr6 [r/w] b, h ----1000 ? 000528 h ? 00052c h epfrc [r/w] b, h -----000 epfrd [r/w] b, h 00000000 epfre [r/w] b, h 00000000 ? 000530 h ? 000534 h to 000550 h ? reserved
mb91345 series 47 (continued) address register block 0123 000554 h ttcr0 [r/w] b, h, w 11110000 ? tstpr0 [r] b, h, w 00000000 timing generator 000558 h comp0 [r/w] b, h, w 00000000 comp2 [r/w] b, h, w 00000000 comp4 [r/w] b, h, w 00000000 comp6 [r/w] b, h, w 00000000 00055c h ttcr1 [r/w] b, h, w 11110000 ? tstpr1 [r] b, h, w 00000000 000560 h comp8 [r/w] b, h, w 00000000 comp10 [r/w] b, h, w 00000000 comp12 [r/w] b, h, w 00000000 comp14 [r/w] b, h, w 00000000 000564 h to 000574 h ? reserved 000578 h adtgs [r/w] b ------00 ? ad trigger select 00057c h to 00063c h ? reserved 000640 h asr0 [r/w] 00000000 00000000 acr0 [r/w] 00110x00 00000000 t-unit 000644 h asr1 [r/w] 00000000 xxxxxxxx acr1 [r/w] 0xxx0x00 00x0xxxx 000648 h asr2 [r/w] xxxxxxxx xxxxxxxx acr2 [r/w] xxxx0x00 00x0xxxx 00064c h asr3 [r/w] 00000000 xxxxxxxx acr3 [r/w] 01xx0x00 00x0xxxx 000650 h ? 000654 h to 00065c h ? 000660 h awr0 [r/w] b, h, w 01111111 11111111 awr1 [r/w] b, h, w xxxxxxxx xxxxxxxx 000664 h awr2 [r/w] b, h, w xxxxxxxx xxxxxxxx awr3 [r/w] b, h, w xxxxxxxx xxxxxxxx 000668 h to 00067c h ? 000680 h cser [r/w] b, h, w 00000001 ? tcr [w] b, h, w 0000xxxx 000684 h ? 000688 h to 0007f8 h ? not used
mb91345 series 48 (continued) address register block 0123 0007fc h ? modr [w] xxxxxxxx ? ? 000800 h to 000afc h ? not used 000b00 h ests0 [r/w] b x0000000 ests1 [r/w] b xxxxxxxx ests2 [r] b 1xxxxxxx ? dsu (evaluation chip only) 000b04 h ectl0 [r/w] b 0x000000 ectl1 [r/w] b 00000000 ectl2 [w] b 000x0000 ectl3 [r/w] b 00x00x11 000b08 h ecnt0 [w] b xxxxxxxx ecnt1 [w] b xxxxxxxx eusa [w] b xxx00000 edtc [w] b 0000xxxx 000b0c h ewpt [r] h 00000000 00000000 ectl4 [r] ([r/w]) b -0x00000 ectl5 [r] ([r/w]) b ----000x 000b10 h edtr0 [w] h xxxxxxxx xxxxxxxx edtr1 [w] h xxxxxxxx xxxxxxxx 000b14 h to 000b1c h ? 000b20 h eia0 [w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b24 h eia1 [w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b28 h eia2 [w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b2c h eia3 [w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b30 h eia4 [w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b34 h eia5 [w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b38 h eia6 [w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b3c h eia7 [w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b40 h edta [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b44 h edtm [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b48 h eoa0 [w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
mb91345 series 49 (continued) address register block 0123 000b4c h eoa1 [w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx dsu (evaluation chip only) 000b50 h epcr [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b54 h epsr [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b58 h eiam0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b5c h eiam1 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b60 h eoam0/eodm0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b64 h eoam1/eodm1 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b68 h eod0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b6c h eod1 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b70 h to 000ffc h ? reserved 001000 h dmasa0 [r/w] 00000000 00000000 00000000 00000000 dmac 001004 h dmada0 [r/w] 00000000 00000000 00000000 00000000 001008 h dmasa1 [r/w] 00000000 00000000 00000000 00000000 00100c h dmada1 [r/w] 00000000 00000000 00000000 00000000 001010 h dmasa2 [r/w] 00000000 00000000 00000000 00000000 001014 h dmada2 [r/w] 00000000 00000000 00000000 00000000 001018 h dmasa3 [r/w] 00000000 00000000 00000000 00000000 00101c h dmada3 [r/w] 00000000 00000000 00000000 00000000 001020 h dmasa4 [r/w] 00000000 00000000 00000000 00000000 001024 h dmada4 [r/w] 00000000 00000000 00000000 00000000 001028 h to 006ffc h ? reserved
mb91345 series 50 (continued) * : refer to ?hardware manual? for initial value. address register block 0123 007000 h flcr [r/w] 01101000 ? flash interface 007004 h flwc [r/w] 00110011 ? 007008 h to 007019 h ? reserved 007020 h wren [r/w] 00000000 ? 007024 h to 00702c h ? 007030 h wa0 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx flash interface 007034 h wd0 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 007038 h wa1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00703c h wd1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 007040 h wa2 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 007044 h wd2 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 007048 h wa3 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx flash interface 00704c h wd3 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 007050 h wa4 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 007054 h wd4 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 007058 h wa5 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00705c h wd5 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 007060 h wa6 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 007064 h wd6 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 007068 h wa7 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00706c h wd7 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
mb91345 series 51 vector table (continued) interrupt factor interrupt no. interrupt level offset address of tbr default dma transfer dmac stop factor decimal hexa- decimal reset 0 00 ? 3fc h 000ffffc h ? mode vector 1 01 ? 3f8 h 000ffff8 h ? system reserved 2 02 ? 3f4 h 000ffff4 h ? system reserved 3 03 ? 3f0 h 000ffff0 h ? system reserved 4 04 ? 3ec h 000fffec h ? system reserved 5 05 ? 3e8 h 000fffe8 h ? system reserved 6 06 ? 3e4 h 000fffe4 h ? coprocessor absent trap 7 07 ? 3e0 h 000fffe0 h ? coprocessor error trap 8 08 ? 3dc h 000fffdc h ? inte instruction 9 09 ? 3d8 h 000fffd8 h ? instruction break exception 10 0a ? 3d4 h 000fffd4 h ? operand break trap 11 0b ? 3d0 h 000fffd0 h ? step trace trap 12 0c ? 3cc h 000fffcc h ? nmi request (tool) 13 0d ? 3c8 h 000fffc8 h ? undefined instruction exception 14 0e ? 3c4 h 000fffc4 h ? nmi request 15 0f 15 (f h ) fixed 3c0 h 000fffc0 h ? external interrupt 0 16 10 icr00 3bc h 000fffbc h ? external interrupt 1 17 11 icr01 3b8 h 000fffb8 h ? external interrupt 2 18 12 icr02 3b4 h 000fffb4 h ? external interrupt 3 19 13 icr03 3b0 h 000fffb0 h ? external interrupt 4 20 14 icr04 3ac h 000fffac h ? external interrupt 5 21 15 icr05 3a8 h 000fffa8 h ? external interrupt 6 22 16 icr06 3a4 h 000fffa4 h ? external interrupt 7 23 17 icr07 3a0 h 000fffa0 h ? reload timer 0 24 18 icr08 39c h 000fff9c h reload timer 1 25 19 icr09 398 h 000fff98 h reload timer 2 26 1a icr10 394 h 000fff94 h uart0 rx/i 2 c0 status 27 1b icr11 390 h 000fff90 h stop uart0 tx 28 1c icr12 38c h 000fff8c h uart1 rx/i 2 c1 status 29 1d icr13 388 h 000fff88 h stop uart1 tx 30 1e icr14 384 h 000fff84 h uart2 rx/i 2 c2 status 31 1f icr15 380 h 000fff80 h stop uart2 tx 32 20 icr16 37c h 000fff7c h
mb91345 series 52 (continued) interrupt factor interrupt no. interrupt level offset address of tbr default dma transfer dmac stop factor decimal hexa- decimal uart3 rx/tx/sx 33 21 icr17 378 h 000fff78 h ? uart4 rx/tx/sx 34 22 icr18 374 h 000fff74 h ? uart5 rx/tx/sx 35 23 icr19 370 h 000fff70 h ? uart6 rx/tx/sx 36 24 icr20 36c h 000fff6c h ? uart7 rx/tx/sx 37 25 icr21 368 h 000fff68 h ? uart8 rx/tx/sx 38 26 icr22 364 h 000fff64 h ? uart9 rx/tx/sx 39 27 icr23 360 h 000fff60 h ? uart10 rx/tx/sx 40 28 icr24 35c h 000fff5c h ? a/d converter 0 41 29 icr25 358 h 000fff58 h a/d converter 1 42 2a icr26 354 h 000fff54 h pwc (measurement complet- ed, overflow) 43 2b icr27 350 h 000fff50 h ? system reserved 44 2c icr28 34c h 000fff4c h ? up/down counter 1 45 2d icr29 348 h 000fff48 h ? up/down counter 2, 3 46 2e icr30 344 h 000fff44 h ? timebase timer overflow 47 2f icr31 340 h 000fff40 h ? ppg 0/ppg 1/ppg 4/ppg 5 48 30 icr32 33c h 000fff3c h ? ppg 2/ppg 3/ppg 6/ppg 7 49 31 icr33 338 h 000fff38 h ? ppg 8/ppg 9/ppg c/ppg d 50 32 icr34 334 h 000fff34 h ? ppg a/ppg b/ppg e/ppg f 51 33 icr35 330 h 000fff30 h ? free running timer 0 52 34 icr36 32c h 000fff2c h ? free running timer 1 53 35 icr37 328 h 000fff28 h ? input capture 0/ input capture 1/ input capture 2/ input capture 3 54 36 icr38 324 h 000fff24 h ? input capture 4/ input capture 5/ input capture 6/ input capture 7 55 37 icr39 320 h 000fff20 h ? output compare 0/ output compare 1/ output compare 2/ output compare 3 56 38 icr40 31c h 000fff1c h ? output compare 4/ output compare 5/ output compare 6/ output compare 7 57 39 icr41 318 h 000fff18 h ?
mb91345 series 53 (continued) interrupt factor interrupt no. interrupt level offset address of tbr default dma transfer dmac stop factor deci- mal hexa- decimal system reserved 58 3a icr42 314 h 000fff14 h ? external interrupt 8 to external interrupt 15 59 3b icr43 310 h 000fff10 h ? external interrupt 16 to external interrupt 23 60 3c icr44 30c h 000fff0c h ? up/down counter 0 61 3d icr45 308 h 000fff08 h ? dma (0 channel to 4 channels) 62 3e icr46 304 h 000fff04 h ? delayed interrupt activation 63 3f icr47 300 h 000fff00 h ? system reserved (used by realos) 64 40 ? 2fc h 000ffefc h ? system reserved (used by realos) 65 41 ? 2f8 h 000ffef8 h ? system reserved 66 42 ? 2f4 h 000ffef4 h ? system reserved 67 43 ? 2f0 h 000ffef0 h ? system reserved 68 44 ? 2ec h 000ffeec h ? system reserved 69 45 ? 2e8 h 000ffee8 h ? system reserved 70 46 ? 2e4 h 000ffee4 h ? system reserved 71 47 ? 2e0 h 000ffee0 h ? system reserved 72 48 ? 2dc h 000ffedc h ? system reserved 73 49 ? 2d8 h 000ffed8 h ? system reserved 74 4a ? 2d4 h 000ffed4 h ? system reserved 75 4b ? 2d0 h 000ffed0 h ? system reserved 76 4c ? 2cc h 000ffecc h ? system reserved 77 4d ? 2c8 h 000ffec8 h ? system reserved 78 4e ? 2c4 h 000ffec4 h ? system reserved 79 4f ? 2c0 h 000ffec0 h ? used by int instruction 80 to 255 50 to ff ? 2bc h to 000 h 000ffebc h to 000ffc00 h ?
mb91345 series 54 electrical characteristics 1. absolute maximum rating * : the parameter is based on v ss = av ss = 0.0 v. warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. 2. recommended operating conditions (v ss = av ss = 0) warning: the recommended operating conditions are requir ed in order to ensure the normal operation of the semiconductor device. all of the device?s electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max power supply voltage * v cc v ss ? 0.5 v ss + 4.0 v analog power supply voltage * av cc v ss ? 0.3 v ss + 4.0 v input voltage * v i v ss ? 0.3 v ss + 4.0 v analog pin input voltage * v ia v ss ? 0.3 avcc + 0.5 v storage temperature tstg ? 40 + 125 c parameter symbol value unit min max operating temperature ta ? 40 + 85 c power supply voltage v cc 3.0 3.6 v analog power supply voltage av cc 3.0 v cc v
mb91345 series 55 3. dc characteristics (v cc = av cc = 3.0 v to 3.6 v, v ss = av ss = 0 v, ta = ? 40 c to + 85 c) * : current when a/d converter is not operating and the cpu is in stop mode. parameter sym- bol pin conditions value unit remarks min typ max power supply current i cc vcc during normal operation ta = + 25 c fcp = 50 mhz, fcpp = 25 mhz ? 65 80 ma i ccs sleep mode during normal operation ta = + 25 c fcp = 50 mhz, fcpp = 25 mhz ? 30 35 ma i cch in stop mode ta = + 25 c, fclk = 0 ? 66 390 a in stop mode ta = + 45 c, fclk = 0 ? 140 760 a ?h? level input voltage v ih ?? v cc 0.7 ? v cc v p20 to p27, p30 to p37, p40 to p47 ?l? level input voltage v il ?? v ss ? v cc 0.3 v p20 to p27, p30 to p37, p40 to p47 ?h? level input voltage v ih ?? v cc 0.8 ? v cc v ?l? level input voltage v il ?? v ss ? v cc 0.2 v ?h? level output voltage v oh ? i oh = ? 4 ma v cc ? 0.5 ? v cc v ?l? level output voltage v ol ? i ol = 4 ma v ss ? 0.4 v input leak current i il ?? ? 5 ? + 5 a a/d power supply current (analog + digital) ?? ? ? 7.2 ? ma at operating a/d 2 unit ?? ? ? ? 5 a at power down operation* a/d reference power supply current (avrh to v ss ) ?? ? ? 940 ? a at operating a/d 2 unit avrh = 3.0 v, vss = 0.0 v ?? ? ? ? 10 a at power down operation*
mb91345 series 56 4. ac characteristics (1) main clock input standard (v cc = av cc = 3.0 v to 3.6 v, v ss = av ss = 0 v, ta = ? 40 c to + 85 c) parameter sym- bol pin condi- tions value unit remarks min typ max clock frequency f c x0 ? 12.5 mhz input clock cycle t cyl ?? 80 ? ns input clock pulse width ? p wh /t cyl p wl /t cyl 40 ? 60 % input clock rise time and fall time t cf t cr ??? 5 ns in external clock internal operating clock frequency f cp ?? ?? 50 mhz cpu core operation clock peripheral clock cycle time t cycp ?? 30 ?? ns peripheral clock is derived from internal operating clock divided by 1/1 to 1/16. x0 0. 8 v cc 0. 8 v cc v ss + 0.4 v ss + 0.4 0. 8 v cc t cyl p wl p wh t cr t cf
mb91345 series 57 (2) pll oscillation stabilization wait time (lock up time) (v cc = av cc = 3.0 v to 3.6 v, v ss = av ss = 0 v, ta = ? 40 c to + 85 c) (3) reset input standard (v cc = av cc = 3.0 v to 3.6 v, v ss = av ss = 0 v, ta = ? 40 c to + 85 c) notes : ? t cp is cycle time for cpu operation clock (clkb) . ? for power-on, input init = ?l? more than regulator voltage stabi lization wait time. if the oscillation stabilization wait time of used oscillator takes more ti me than regulator voltage stabilization wait time, input init = ?l? until the oscillation is stable. parameter symbol value unit remarks min max pll oscillation stabilization wait time (lock up time) t lock 500 ? s wait time until the pll oscillation is stable. parameter symbol pin condi- tions value unit remarks min max reset input time (except power-on) t intl init ? t cp 10 ? ns init v il v il t intl
mb91345 series 58 (4) uart timing (v cc = av cc = 3.0 v to 3.6 v, v ss = av ss = 0 v, ta = ? 40 c to + 85 c) notes : ? ac rating in clk synchronous mode ? t cycp is the peripheral clock cycle time. parameter sym- bol pin conditions value unit min max serial clock cycle time t scyc sck0 to sck10 internal shift clock operation 4 t cycp ? ns sck sot delay time t slov sck0 to sck10, sot0 to sot10 ? 20 + 20 ns valid sin sck t ivsh sck0 to sck10, sin0 to sin10 30 ? ns sck valid sin hold time t shix sck0 to sck10, sin0 to sin10 20 ? ns serial clock ?h? pulse width t shsl sck0 to sck10 external shift clock operation 2 t cycp ? ns serial clock ?l? pulse width t slsh sck0 to sck10 2 t cycp ? ns sck sot delay time t slov sck0 to sck10, sot0 to sot10 ? 30 ns valid sin sck t ivsh sck0 to sck10, sin0 to sin10 20 ? ns sck valid sin hold time t shix sck0 to sck10, sin0 to sin10 20 ? ns
mb91345 series 59 internal shift clock mode external shift clock mode s ck0 to s ck10 s ot0 to s ot10 s in0 to s in10 t s cyc t s lov t iv s h t s hix v ol v oh v ol v oh v ol v oh v ol v oh v ol s ck0 to s ck10 s ot0 to s ot10 s in0 to s in10 t s lov t s l s h t s h s l t iv s h t s hix v oh v ol v oh v oh v ol v ol v oh v ol v oh v ol
mb91345 series 60 (5) free-run timer clock, reload timer event input , up down counter input , input capture input, interrupt input timing (v cc = av cc = 3.0 v to 3.6 v, v ss = av ss = 0 v, ta = ? 40 c to + 85 c) *1 : t cycp is cycle time for peripheral clock. *2 : except in stop time *3 : in stop time parameter sym- bol pin conditions value unit remarks min max input pulse width t tiwh t tiwl frck0, frck1, tin0, tin1, tin2, ic0, ic1, ain0, ain1, bin0, bin1, zin0, zin1 ? t cycp 2 ? ns *1 int0 to int23 t cycp 3 ? ns *2 1.0 ? s*3 t tiwh t tiwl v ih v ih v il v il frck0, frck1, tin0, tin1, tin2, ic0, ic1, ain0, ain1, bin0, bin1, zin0, zin1, int0 to int2 3
mb91345 series 61 (6) a/d trigger input timing (v cc = av cc = 3.0 v to 3.6 v, v ss = av ss = 0 v, ta = ? 40 c to + 85 c) * : t cycp is the peripheral clock cycle time. parameter sym- bol pin conditions value unit remarks min max a/d trigger input (falling time) t tadtg adtrg0, adtrg0-2, adtrg1, adtrg1-2 ? t cycp 2 ? ns * t tadtg v ih v il v il adtrg0, adtrg0-2, adtrg1, adtrg1-2
mb91345 series 62 (7) i 2 c timing ? at master mode operating (v cc = av cc = 3.0 v to 3.6 v, v ss = av ss = 0 v, ta = ? 40 c to + 85 c) *1 : m = resource clock cycle (ns) *2 : a high-speed mode i 2 c bus device can be used for a typical mode i 2 c bus system as long as the device satisfies a requirement of ?t sudat 250 ns?. when a device does not extend the ?l? period of the scl signal, the next data must be outputted to the sda line within 1250 ns (maximum sda/scl rise time + t sudat ) in which the scl line is released. *3 : for use at over 100 khz, set t he resource clock to at least 6 mhz. *4 : r and c represent the pull-up resistor and load capa citor of the scl and sda output lines, respectively. parameter symbol conditions typical mode high-speed mode* 3 unit remarks min max min max scl clock frequency f scl r = 1 k ? c = 50 pf *4 01000400khz ?l? period of scl clock t low 4.7 ? 1.3 ? s ?h? period of scl clock t high 4.0 ? 0.6 ? s scl sda output delay time t dldat ? 5 m *1 ? 5 m *1 ns bus free time between [stop condition] and [start condition] t bus 4.7 ? 1.3 ? s sda data input hold time (vs. scl ) t hddat 2 m *1 ? 2 m *1 ? s sda data input setup time (vs. scl ) t sudat 250 ? 100 *2 ? ns setup time of [repeat start condition] scl sda t susta 4.7 ? 0.6 ? s hold time of [repeat start condition] sda scl t hdsta 4.0 ? 0.6 ? s after that, the first clock pulse is generated. setup time of [stop condition] scl sda t susto 4.0 ? 0.6 ? s
mb91345 series 63 ? at slave mode operating (v cc = av cc = 3.0 v to 3.6 v, v ss = av ss = 0 v, ta = ? 40 c to + 85 c) *1 : m = resource clock cycle (ns) *2 : a high-speed mode i 2 c bus device can be used for a typical mode i 2 c bus system as long as the device satisfies a requirement of ?t sudat 250 ns?. when the device does not extend the ?l? period of the scl signal, the next data must be outputted to the sda line within 1250 ns (maximum sda/scl rise time + t sudat ) in which the scl line is released. *3 : for use at over 100 khz, set t he resource clock to at least 6 mhz. *4 : r and c represent the pull-up resistor and load capa citor of the scl and sda output lines, respectively. parameter symbol conditions typical mode high-speed mode* 3 unit remarks min max min max scl clock frequency f scl r = 1 k ? c = 50 pf *4 01000400khz ?l? period of scl clock t low 4.7 ? 1.3 ? s ?h? period of scl clock t high 4.0 ? 0.6 ? s scl sda output delay time t dldat ? 5 m *1 ? 5 m *1 ns bus free time be- tween [stop condi- tion and start condition] t bus 4.7 ? 1.3 ? s sda data input hold time (vs. scl ) t hddat 2 m *1 ? 2 m *1 ? s sda data input setup time (vs. scl ) t sudat 250 ? 100 *2 ? ns setup time of [repeat start condition] scl sda t susta 4.7 ? 0.6 ? s hold time of [repeat start condition] sda scl t hdsta 4.0 ? 0.6 ? s after that, the first clock pulse is generated. setup time of [stop condition] scl sda t susto 4.0 ? 0.6 ? s
mb91345 series 64 (8) regulator voltage wait time (v cc = av cc = 3.0 v to 3.6 v, v ss = av ss = 0 v, ta = ? 40 c to + 85 c) parameter symbol value unit remarks min max regulator voltage wait time t reg 250 ? s wait time until the regulator voltage is stable
mb91345 series 65 5. electrical characteristics for the a/d converter (v cc = av cc = 3.0 v to 3.6 v, v ss = av ss = 0 v, avrh = 3.0 v to 3.6 v, ta = ? 40 c to + 85 c) *1 : measured in the cpu sleep state. *2 : depends on the clock cycle su pplied to the peripheral resource. *3 : no external load *4 : current when the a/d converter is not operating and the cpu is in stop mode parameter value unit remarks min typ max resolution ?? 10 bit total error* 1 ? 3.0 ?+ 3.0 lsb av cc = 3.3 v, avrh = 3.3 v nonlinear error* 1 ? 2.5 ?+ 2.5 lsb differential linear error* 1 ? 1.9 ?+ 1.9 lsb zero transition voltage* 1 ? 1.5 + 0.5 + 2.5 lsb full transition voltage* 1 avrh ? 3.5 avrh ? 1.5 avrh + 0.5 lsb minimum comparison time* 2 0.6 ?? s not including sampling time minimum sampling time* 2 0.3* 3 ?? s conversion time 0.9* 3 1.1 ? s power supply current (analog + digital) ? 7.2 ? ma at operating a/d 2 unit ?? 5 a at power down operation* 4 reference power supply current (between avrh and avrl) ? 940 ? a at operating a/d 2 unit avrh = 3.0 v, avrl = 0.0 v ?? 10 a at power down operation* 4 analog input capacitance ?? 20 pf interchannel disparity ?? 4lsb
mb91345 series 66 ? about the external impedance of th e analog input and its sampling time a/d converter with sample and hold circuit. if the exter nal impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sampling and hold capacitor is insuff icient, adversely affecting a/d conversion precision. therefore, to satisfy the a/ d conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external im pedance so that the sampling time is longer than the minimum value. if the sampling time cannot be sufficient , connect a capacitor of about 0.1 f to the analog input pin. r c comp a r a tor analog input circuit model analog input pin during sampling : on note : the values are reference values. rc mb91f345b/f346b 1.5 k ? (max) 20.0 pf (max) 100 90 80 70 60 50 40 30 20 10 0 35 30 25 20 15 10 5 0 0 1 2 34 5 6 7 8 0 2 4 6 8 10 12 14 16 18 20 the relationship between the external impedance and minimum sampling time minimum sampling time ( s) minimum sampling time ( s) external impedance (k ? ) external impedance (k ? ) [external impedance = 0 k ? to 100 k ? ] [external impedance = 0 k ? to 20 k ? ]
mb91345 series 67 ? a/d converter block electrical characteristics resolution analog variations recognized by an a/d converter. linearity error deviation of actual conversion characteristics from an ideal line, which is ac ross zero-transition point (?00 0000 0000? ?00 0000 0001?) and full-scale tran sition point (?11 1111 1110? ?11 1111 1111?). differential linearity error deviation from ideal value of input voltage, wh ich is required for changing output code by 1 lsb. total error difference between actual value and ideal value. the e rror includes zero-transition error, full-scale transition error, and linearity error. (continued) 3ff h 001 h 3fd h 004 h 003 h 002 h 3fe h 0.5 lsb' av ss avrh {1 lsb' ( n ? 1 ) + 0.5 lsb'} 1.5 lsb' analog input total error digital output actual characteristic v nt (actual measured value) ideal characteristics actual characteristic v nt : transition voltage for digi tal output to change from (n + 1) h to n h . v ot ' (ideal value) = av ss + 0.5 lsb' [v] v fst ' (ideal value) = avrh ? 1.5 lsb' [v] 1 lsb' (ideal value) = avrh ? av ss [v] 1024 total error of digital output n = v nt ? {1 lsb' (n ? 1) + 0.5 lsb'} 1 lsb'
mb91345 series 68 (continued) about errors as |avrh ? av ss | becomes smaller, values of relative errors grow larger. n ? 2 h n ? 1 h n h n + 1 h av ss avrh 3 ff h 001 h 3 fd h 004 h 00 3 h 002 h 3 fe h av ss avrh { 1 l s b' ( n ? 1 ) + v ot } analog input analog input differential linearity error linearity error digital output digital output actual conversion characteristic v fst (actual measured value) v nt (actual measured value) actual conversion characteristic ideal characteristics v ot (actual measured value) ideal characteristics actual conversion characteristic actual conversion characteristic v nt (actual measured value) v fst (actual measured value) v ot : transition voltage for digita l output to change from (000) h to (001) h . v fst : transition voltage for digita l output to change from (3fe) h to (3ff) h . linearity error of digital output n = v nt ? {1 lsb' (n ? 1) + v ot } [lsb] 1 lsb' differential linearity e rror of digital output n = v (n + 1) t ? v nt ? 1[lsb] 1 lsb' 1 lsb = v fst ? v ot [v] 1022
mb91345 series 69 6. flash memory write/erase characteristics (v cc = av cc = 3.0 v to 3.6 v, v ss = av ss = 0 v, ta = ? 40 c to + 85 c) * : this value comes from the technology qualification (using arrhenius equation to translate high temperature measurements into normalized value at + 55 c) . parameter conditions value unit remarks min typ max sector erase time ?? 115s excludes 00 h programming prior erasure byte write time ?? 6100 s not including system-level overhead time chip write time ?? 3.4 56 s not including system-level overhead time erase/write cycle ? 10000 ?? cycle flash memory data retain period average ta = + 55 c 10 ?? year *
mb91345 series 70 ordering information part number package MB91F345BPFT-GE1 mb91f346bpft-ge1 100-pin plastic tqfp (fpt-100p-m18)
mb91345 series 71 package dimensions please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html 100-pin pl as tic tqfp le a d pitch 0.40 mm p a ck a ge width p a ck a ge length 12.0 12.0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.20 mm max weight 0.40g code(reference) p-tfqfp100-12 12-0.40 100-pin pl as tic tqfp (fpt-100p-m1 8 ) (fpt-100p-m1 8 ) c 200 3 fujit s u limited f100029 s -c- 3 -4 index 12.000.10(.472.004) s q 14.000.20(.551.00 8 ) s q "a" 0.1450.055 (.006.002) 51 75 50 76 26 100 1 lead no. 25 0.40(.016) 0.1 8 0.05 (.007.002) 0.07(.002) m 0 ? ~ 8 ? 0.25(.010) 0.600.15 (.024.006) 0.100.05 (.004.002) ( s t a nd off) det a il s of "a" p a rt 0.0 8 (.00 3 ) (.04 3 .004) 1.100.10 * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 )pin s width do not incl u de tie ba r c u tting rem a inder.
mb91345 series f0703 the information for microcontroller suppor ts is shown in the following homepage. http://www.fujitsu.com/global/s ervices/microelectronics/produ ct/micom/support/index.html fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited business promotion dept.

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